Method for making a SOI semiconductor substrate with thin active semiconductor layer

ABSTRACT

The invention concerns a method comprising: 1) a first phase including steps which consist in forming in the upper part of a first initial semiconductor substrate a first layer of insulating material above a sectional plane of said first substrate, contacting the first layer of insulating material with the insulating upper part of a second initial substrate, so as to form a single layer of insulating material, a break at the sectional plane, so as to obtain an intermediate semiconductor substrate on the single insulating material layer; then, 2) in a second phase which consists in forming in the intermediate semiconductor substrate an additional insulating material layer adjacent to the single insulating material and topped with an upper layer of a final semiconductor substrate.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims priority from prior PCTApplication PCT-FR01-01960 filed on Jun. 21, 2001, which claims priorityon prior French Patent Application No. 0008094 Filed on Jun. 23, 2000the entire disclosure of both applications which are hereby incorporatedby reference in there entirety.

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

Not Applicable

INCORPORATION-BY-REFERENCE OF MATERIAL SUBMITTED ON A COMPACT DISK

Not Applicable

BACKGROUND OF THE INVENTION

(1) Field of the Invention

The present invention relates in general to integrated circuits and moreparticularly to the manufacture of a device of the SOI (Silicon OnInsulator) type comprising a layer of semiconductor material on a layerof insulating material.

(2) Description of the Related Art

The manufacture of SOI (Silicon On Insulator) devices comprising a layerof semiconductor material on a layer of insulating material is known.These SOI-type devices are more particularly intended to be used forproducing devices of the type which are fully depleted of chargecarriers in the channel region, also called fully-depleted devices, inwhich the thickness of the silicon-containing semiconductor substrate,also called the active layer, defines inter alia the threshold voltageof MOS-type transistors and is of great importance.

A major difficulty in the use of fully-depleted assemblies is how toproduce thin layers of silicon-containing semiconductor substrate, on alayer of an insulating material with good control and sufficientreproducibility of the thickness of this active layer between twodifferent manufacturing batches.

To perform properly, fully-depleted structures require active layerswith a thickness of about 5 to 30 nanometers depending on the thresholdvoltage that it is desired to obtain and on the transistor gatedimensions. For example, for 0.1 μm technology, the ideal siliconthickness is about 15 nm for a threshold voltage of around 0.35 volts.Any deviation from planarity of the active layer and any difference inthickness of the active layer between two manufacturing batches resultin a corresponding variation in the threshold voltage. In general, onany given active layer, the deviation from planarity is small (about afew percent), but from one batch to another the difference in thicknessmay be much greater.

The known techniques for fabricating SOI-type devices all have a numberof drawbacks, particularly a low production yield, the formation ofrelatively thick active layers, of mediocre uniformity and difficult toreproduce from one assembly to another, and consequently having athreshold voltage that cannot be easily controlled.

One first SOI-type device fabrication process, known as “SIMOX”technology, consists in forming an SiO₂ layer buried in a siliconsubstrate by a step of high-dose oxygen implantation followed byannealing at a temperature above 1300° C. The drawbacks of this processare in particular the high cost of fabricating the trenches, the crystaldefects generated in the silicon layer by high-dose, high-energy oxygenimplantation, the small thickness of the buried insulation layer and thedefects (holes) within the buried insulation layer.

Finally, this process, because the thicknesses of the silicon and buriedsilicon oxide layers are determined by the implantation process, that isto say a massive implantation of oxygen at high energy and with a highdose, makes it difficult to achieve thicknesses of less than 50 nm inthe case of the thin residual silicon layer.

A second process, known as “BESOI” technique consists in producing anSOI-type device by forming, on a surface of a first silicon substrate, athin SiO₂ film, joining this first substrate, via the thin SiO₂ film, toa second silicon substrate and finally removing, by mechanical grindingand polishing, part of one of the silicon substrates in order to form athin silicon layer above the buried silicon oxide layer. The siliconoxide layer on the first silicon substrate is formed by a succession ofsteps which are: oxidation of the surface of this first substrate andthen the etching of the oxide layer formed in order to obtain thedesired thickness.

This process makes it possible to obtain only buried silicon oxidelayers and silicon layers on the buried silicon oxide which arerelatively thick because of the poor control of the etching process.Furthermore, the thin layers obtained by this process have pooruniformity as a result of the use of mechanical steps which in generalgenerate ups and downs on the surface of the active layer.

A third process, known as “SMARTCUT” technology, consists in forming athin silicon oxide layer by oxidation on a first silicon substrate andthen implanting, under the thin silicon oxide layer, H⁺ ions into thisfirst silicon substrate in order to form, within it, a plane ofcavities. Next, this first substrate is bonded to a second pre-oxidizedsilicon substrate via the thin silicon oxide layer. The assembly thusformed is then heat treated for the purpose of converting the plane ofcavities into a splitting plane.

This process makes it possible to recover, on the one hand, an SOIassembly and, on the other hand, a reusable silicon substrate and itrequires the implantation of a high dose of hydrogen atoms. Despite theuse of hydrogen atoms which are smaller in size than the oxygen atoms ofthe SIMOX process, the surface of the thin silicon layer obtained isalso damaged. Furthermore, the use of this technique does not in generalmake it possible to obtain thin silicon layer thicknesses of less thanapproximately 50 nm. In the SOI assemblies thus obtained, the thicknessof the silicon active layer formed is determined by the hydrogenimplantation, allowing the initial substrate to be cut and this layerthen to be finely polished. The deviation from planarity caused by thisprocess is approximately 5 nm, whatever the thickness of the finallayer. It therefore becomes a major drawback for thicknesses of lessthan 50 nm. In addition, the variation in thickness from one wafer toanother may be about 25% to 40% of the mean thickness of a batch ofwafers, for example in the case of nominal thicknesses of less than 50nm, thereby constituting a major handicap when producing complexcircuits because of the difference in threshold voltage resulting fromthe difference in thickness.

The above processes are described, in particular, in the article “SOI:Materials to Systems (by A. J. Auberton-Hervé, IEEE, 1996.

According, a need exist to provide a process for fabricating an SOI-typedevice which overcomes the drawbacks of the processes of the prior art.

BRIEF SUMMARY OF THE INVENTION

In particular, the present invention provides a process for fabricatingan SOI assembly which makes it possible to obtain silicon-containingsemiconductor substrates, resting on a layer of insulating material,which are very thin, including for thicknesses of insulatedsemiconductor of less than 50 nm, are of very good uniformity and havevery good reproducibility, from an SOI-type device comprising a layer ofsemiconductor material on a layer of insulating material.

According to one aspect of the invention, this process for fabricating adevice of the Silicon-On-Insulator (SOI) type, comprising a layer ofsemiconductor material on a layer of insulating material, comprises

-   -   1) a first phase comprising the following steps:        -   a) formation in the upper part of a first initial            semiconductor substrate of a first layer of insulating            material on top of a splitting plane of this first            substrate,        -   b) contacting of the first layer of insulating material with            the insulating upper part of a second initial substrate so            as to form a single layer of insulating material and        -   c) cutting, in the splitting plane, so as to obtain an            intermediate semiconductor substrate on the single layer of            insulating material; and then    -   2) a second phase comprising the formation in the intermediate        semiconductor substrate of an additional layer of insulating        material contiguous with the single layer of insulating material        and surmounted by an upper layer of final semiconductor        substrate.

During the first phase of the process, the splitting plane may be formedbefore or after the first layer of insulating material. This first layerof insulating material may be especially formed by oxidation, nitridingor deposition. The second initial substrate may be of any electricaltype. If it is insulating, for example made of glass, it will thus notbe necessary to form an insulating upper part. If the second initialsubstrate is a semiconductor, the insulating upper part could beespecially formed by oxidation, nitriding or deposition.

One of the advantages of the proposed process is that the implantationof the species serving to generate the additional layer of insulatingmaterial adjoining the single layer of insulating material makes itpossible to position, accurately and completely reproducibly, thedesired species with respect to the surface via which the ion beamenters the intermediate semiconductor substrate. The only variationcaused by this process is a variation in the position of the implantedspecies, which depends only on the implanted species and on theimplantation energy used. The position of the species implanted into theintermediate semiconductor substrate therefore does not depend on thethickness of this substrate but only on the implantation energy for agiven species being implanted.

Since the implantation energy is relatively simple to control, it thusbecomes extremely easy to control the depth of implantation of the ionspecies. The reproducibility of the process stems from the fact that allimplantations, for a given species and for a given energy, will takeplace at the same depth, therefore making it possible to obtain an upperlayer of final semiconductor substrate which is perfectly reproducible,whatever the difference in thickness of the intermediate semiconductorsubstrates of different initial SOI-type devices subjected to theimplantation.

This technique therefore improved control of the active layer thickness,with remarkable reproducibility and extreme reliability.

The invention is also noteworthy in that it uses, in the first phase, aphase of the “SMARTCUT technology” type and in that it makes it possibleto remedy the principal drawback of this technique (the impossibility ofobtaining particularly small thicknesses of the silicon substrate, andthe substantial scatter in the thicknesses obtained) by combining itwith the second phase of forming an additional insulating layer.

Preferably, the formation in the intermediate semiconductor substrate ofthis additional layer of insulating material is produced by means ofoxygen and/or nitrogen implantation into the intermediate semiconductorsubstrate followed by a heat treatment.

According to a preferred method of implementing the invention, theoxygen and/or nitrogen implantation is carried out at an energy ofgreater than 2 keV.

Preferably, the oxygen and/or nitrogen implantation is carried out withdoses of between 10¹⁶ atoms/cm² and 10²⁰ atoms/cm².

According to a preferred method of implementing the invention, thethickness of the layer of final semiconductor substrate is greater than5 nm and is more particularly between 5 nm and 30 nm.

Because of the oxygen and/or nitrogen atom implantation within the thicksilicon-containing semiconductor substrate of the initial SOI assembly,the additional layer of insulating material comprises silicon oxideand/or silicon nitride.

Preferably, the first initial semiconductor substrate comprisessingle-crystal pure silicon, germanium, silicon-germanium alloys of theSi₁−x−Ge_(x) type (where 0<x<1) or carbon-containing silicon-germaniumalloys of the Si_(1−x−y)Ge_(x)C_(y) type (where 0<x<0.95 and 0<y<0.95).

The invention also relates to an integrated circuit comprising anSOI-type device obtained by the process described above.

This electronic circuit may comprise at least one electronic componentchosen from the following list: high-voltage or power diode, transistor,capacitor.

The foregoing and other features and advantages of the present inventionwill be apparent from the following more particular description of thepreferred embodiments of the invention, as illustrated in theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

Further advantages and features of the invention will become apparent onexamining the detailed description of an entirely non-limiting method ofimplementing the process of the invention, illustrated by FIGS. 1 to 10,

FIGS. 1 and 2 are cross-sectional views of the SOI-type device duringthe first phase of a method of implementing the process of theinvention; and

FIGS. 3 to 10 are cross-sectional views of the SOI-type device duringthe second phase of a method of implementing the process of theinvention.

It should be understood that these embodiments are only examples of themany advantageous uses of the innovative teachings herein. In general,statements made in the specification of the present application do notnecessarily limit any of the various claimed inventions. Moreover, somestatements may apply to some inventive features but not to others. Ingeneral, unless otherwise indicated, singular elements may be in theplural and vice versa with no loss of generality.

FIG. 1 shows a first initial semiconductor substrate 0. This firstinitial semiconductor substrate may comprise any type of semiconductormaterial, and may especially comprise single-crystal silicon, germanium,alloys, Si_(1−x)Ge_(x) silicon alloys (where 0<x<1) orSi_(1−x−y)Ge_(x)C_(y) silicon alloys (where 0<x<0.95 and 0<y<0.95).

In this first initial semiconductor substrate 0, a splitting plane isformed, for example by H⁺ ion implantation, said plane being representedby the dotted line in the figure and defining a layer 1 in the firstinitial semiconductor substrate 0. The upper part of the first initialsemiconductor substrate 0 is then oxidized to form a first layer ofinsulating material 3 a on top of the splitting plane.

Likewise, the upper part of a second initial semiconductor substrate 5is oxidized to form a second layer of insulating material 3 b. The twoinitial semiconductor substrates are then brought into contact with eachother via their layer of insulating material 3 a and 3 b in order toform a single layer of insulating material, as illustrated in FIG. 2.

A cutting operation is then carried out in the splitting plane so as toobtain an intermediate semiconductor substrate on the single layer ofinsulating material 3. Next, a chemical-mechanical polishing operationis carried out on the upper surface of the intermediate semiconductorsubstrate so as to remove the defects generated by the ion implantation.

FIG. 3 illustrates the SOI-type device at the end of the first phase ofthe process. This device comprises the intermediate semiconductorsubstrate 1 on the single layer of insulating material 3, which layerrests on the second initial semiconductor substrate 5. The first phaseof the process is consequently a “SMARTCUT technology” type phase.

FIG. 4 also illustrates an SOI-type device at the end of the first phaseof the process, the device comprising the intermediate semiconductorsubstrate 2 on the single layer of insulating material 4, which layerrests on the second initial semiconductor substrate 6.

The devices in FIGS. 3 and 4, although obtained by the same phase of theprocess, have different thicknesses of the intermediate semiconductorsubstrates 1 and 2. The difference in thickness between the intermediatesemiconductor substrates 1 and 2 is depicted in the figures by thedistance δ.

Starting from these assemblies, and in accordance with the second phaseof the process, the species serving to generate the additional layer ofinsulating material is implanted within the intermediate semiconductorsubstrates 1 and 2, the species being chosen from oxygen and/ornitrogen.

FIGS. 5 and 6 illustrate the profile of the implantation peaks 7 and 8of the desired species within the intermediate semiconductor substrates1 and 2. These implantation peaks 7 and 8 are positioned according tothe process at the same depth x in the substrate whatever the thicknessof the intermediate semiconductor substrates 1 and 2. The peaks 7 and 8are therefore implanted in the substrates 1 and 2 with a difference indepth δ with respect to the layers of single insulating material 3 and4. These nitrogen and/or oxygen atoms are preferably implanted withdoses of between 10¹⁶ atoms/cm² and 10²⁰ atoms/cm² at an energy ofgreater than 2 keV. The lowest energy is used for large thicknesses ofthe semiconductor substrate of around 50 nm and may reach severalhundreds of keV in the case of thicknesses of around 500 nm. Theserelatively high doses and these energies furthermore allow theimplantation peaks 7 and 8 to be accurately positioned in theintermediate semiconductor substrates 1 and 2.

Once the implantation has been carried out, the implanted species isactivated so as to create an additional layer of insulating material bymaking the implanted species react with the species of which thesubstrates 1 and 2 are composed. In general, the implanted species isoxygen and/or nitrogen. The layer of additional insulating material thusformed will therefore consist of silicon oxide and/or silicon nitride.Preferably, the activation step will comprise a heat treatment on theassembly thus formed.

FIGS. 7 and 8 illustrate the profile of the layers of additionalinsulating material 9 and 10 which are obtained after heat treatment.The heat treatment makes it possible to form the additional layers ofinsulating material 9 and 10 in the intermediate semiconductorsubstrates 1 and 2. These additional layers of insulating material 9 and10 are produced in the same way and with identical implantationparameters, they are therefore formed at the same depth P in theintermediate semiconductor substrates 1 and 2.

FIGS. 9 and 10 illustrate a cross-sectional view of the SOI-type devicesobtained at the end of the second phase of the process and show theformation of the final semiconductor substrates 11 and 12 from theinitial semiconductor substrates 1 and 2, these final semiconductorsubstrates 11 and 12 having a thickness P greater than 5 nm andpreferably between 5 nm and 30 nm, the said final semiconductorsubstrates 11 and 12 having the same thickness P for both assembliesused.

Thus, two SOI-type devices each comprising a final semiconductorsubstrate, 11 and 12 respectively, and preferably consisting of silicon,resting on a layer of an insulating material, 13 and 14 respectively,are obtained, the said layer of insulating material being composed ofthe single layer of insulating material, 3 and 4 respectively, and ofthe additional layer of insulating material, 7 and 8 respectively, thetwo assemblies having the same thickness P of final semiconductorsubstrate, 11 and 12 respectively.

Although a specific embodiment of the invention has been disclosed, itwill be understood by those having skill in the art that changes can bemade to this specific embodiment without departing from the spirit andscope of the invention. The scope of the invention is not to berestricted, therefore, to the specific embodiment, and it is intendedthat the appended claims cover any and all such applications,modifications, and embodiments within the scope of the presentinvention.

The substrates thus obtained are therefore completely reproducible andparticularly suitable for being used to produce fully-depleted devices.

1. A process for fabricating two or more silicon-on-insulator (SOI) typesemiconductor substrates, wherein each of the substrates include asemiconductor active layer, the process comprising the steps of: formingan insulating layer on top of a support layer; forming asilicon-containing semiconductor substrate with a given thickness on topof the insulating layer; forming both an insulation layer within thesilicon-containing semiconductor substrate, and a residual layer ofsilicon-containing semiconductor on top of the silicon-containingsemiconductor substrate, by performing the steps of: implanting at leastone of nitrogen and oxygen atoms at a predetermined depth in the giventhickness of the silicon-containing semiconductor substrate; andactivating at least one of nitrogen and oxygen atoms through heat tocreate a layer of insulating, material within the silicon-containingsemiconductor substrate and to create a residual layer ofsilicon-containing semiconductor through the reaction with thesilicon-containing semiconductor substrate thereby creating the residuallayer of silicon-containing semiconductor with a predeterminedthickness.
 2. The process according to claim 1, wherein the step offorming an insulating layer includes forming an insulating layercomprised of silicon oxide.
 3. The process according to claim 1, whereinthe step of forming an insulating layer includes forming an insulatinglayer on top of a support layer comprised of at least one of silicon andsilicon alloy.
 4. The process according to claim 1, wherein in the stepof implanting at least one of nitrogen and oxygen atoms includesimplanting both nitrogen and oxygen atoms.
 5. The process according toclaim 4, wherein the step of implanting at least one of nitrogen andoxygen atoms includes implanting at least one of nitrogen and oxygenatoms with an energy of between a 1 keV and 50 keV.
 6. The processaccording to claim 1, wherein the step of activating at least one ofnitrogen and oxygen atoms through heat to create a layer of insulatingmaterial within the silicon-containing semiconductor substrate includescreating an insulating material consisting of at least one of siliconnitride and silicon oxide.
 7. The process according to claim 6, whereinthe step of activating the at least one of nitrogen and oxygen atomsthrough heat to create a layer of insulating material within thesilicon-containing semiconductor substrate and to create the residuallayer of silicon-containing semiconductor through the reaction with thesilicon-containing semiconductor substrate thereby creating the residuallayer of silicon-containing semiconductor with a predetermined thicknessof between 5 nm to 30 nm.
 8. The process according to claim 6, whereinthe step of forming a silicon-containing semiconductor substrate with agiven thickness on top of the insulating layer includes forming asilicon-containing layer using SIMOX technology.
 9. The processaccording to claim 1, wherein the step of activating at least one ofnitrogen and oxygen atoms through heat to create a layer of insulatingmaterial within the silicon-containing semiconductor substrate and tocreate the residual layer of silicon-containing semiconductor throughthe reaction with the silicon-containing semiconductor substrate therebycreating the residual layer of silicon-containing semiconductor with apredetermined thickness of between 5 nm to 100 nm.
 10. The processaccording to claim 1, wherein the step of forming a silicon-containingsemiconductor substrate with a given thickness on top of the insulatinglayer includes forming a silicon-containing semiconductor substratecomprising a single-crystal silicon, polycrystalline silicon,Si_(1−x)Ge_(x) silicon alloys, where 0<x 1 or Si_(1−x−y)Ge_(x)C_(y)silicon alloys, where 0<x<0.95 and 0<y<0.95.
 11. The process accordingto claim 1, wherein the step of forming a silicon-containingsemiconductor substrate with a given thickness on top of the insulatinglayer includes forming a silicon-containing layer using SMARTCUTtechnology.
 12. The process according to claim 1, wherein the step ofimplanting at least one of nitrogen and oxygen atoms includes implantingat least one of nitrogen and oxygen atoms with doses of between 10¹⁷atoms/cm² and 10²⁰ atoms/cm².
 13. The process according to claim 1,wherein the step of activating the at least one of nitrogen and oxygenatoms through heat includes activating the at least one of nitrogen oroxygen atoms through annealing.
 14. A process for fabricating anassembly comprising a silicon-containing semiconductor substrate with alayer of insulating material, the process comprising the steps of:forming a silicon-containing semiconductor substrate on top of a layerof insulating material disposed on a support layer; implanting nitrogenand/or oxygen atoms within the silicon-containing semiconductorsubstrate; and activating the nitrogen and/or oxygen atoms with heatthereby creating an additional layer of insulating material adjacent tothe previously formed insulating layer and creating a residual thinsilicon containing substrate of a predetermined thickness on top of theadditional layer of insulating material.
 15. The process according toclaim 14, wherein the step of activating the nitrogen and/or oxygenatoms with heat creates a residual layer of silicon-containingsemiconductor with a predetermined thickness of between 5 nm to 100 nm.16. The process according to claim 14, wherein the step of activatingthe nitrogen and/or oxygen atoms with heat creates a residual layer ofsilicon-containing semiconductor with a predetermined thickness ofbetween 5 nm to 30 nm.
 17. The process according to claim 14, whereinthe step of implanting nitrogen and/or oxygen atoms includes implantingnitrogen and/or oxygen atoms with an energy of between a 1 keV and 50keV.
 18. The process according to claim 14, wherein the step ofimplanting nitrogen and/or oxygen atoms includes implanting nitrogenand/or oxygen atoms with doses of between 10¹⁷ atoms/cm² and 10²⁰atoms/cm².
 19. The process according to claim 14, wherein the step offorming a silicon-containing semiconductor substrate with a giventhickness on top of the insulating layer includes forming asilicon-containing semiconductor substrate comprising a single-crystalsilicon, polycrystalline silicon, Si_(1−x)Ge_(x) silicon alloys, where0<x<1 or Si_(1−x−y)Ge_(x)C_(y) silicon alloys, where 0<x<0.95 and0<y<0.95.
 20. A process for fabricating an assembly comprising asilicon-containing semiconductor substrate with a layer of insulatingmaterial, the process comprising the steps of: forming asilicon-containing semiconductor substrate on top of a layer ofinsulating material disposed on a support layer; implanting an ionspecies adapted to form an additional layer within thesilicon-containing semiconductor substrate; and activating the ionspecies implanted with heat so that the ion species implanted react withsilicon-containing semiconductor substrate so as to create an additionallayer of insulating material adjacent to the previously formedinsulating layer and so as to create a residual thin silicon containingsubstrate of a predetermined thickness on top of the additional layer ofinsulating material.